Growth substrates for inverted metamorphic multijunction solar cells

ABSTRACT

A method of manufacturing a solar cell by providing a gallium arsenide carrier with a prepared bonding surface; providing a sapphire substrate; bonding the gallium arsenide carrier and the sapphire substrate to produce a composite structure; detaching the bulk of the gallium arsenide carrier from the composite structure, leaving a gallium arsenide growth substrate on the sapphire substrate; and depositing a sequence of layers of semiconductor material forming a solar cell on the growth substrate. For some solar cells, the method further includes mounting a surrogate second substrate on top of the sequence of layers of semiconductor material forming a solar cell; and removing the growth substrate.

REFERENCE TO RELATED APPLICATIONS

This application is related to co-pending U.S. patent application Ser.No. 12/271,127 and Ser. No. 12/271,192 filed Nov. 14, 2008.

This application is related to co-pending U.S. patent application Ser.No. 12/267,812 filed Nov. 10, 2008.

This application is related to co-pending U.S. patent application Ser.No. 12/258,190 filed Oct. 24, 2008.

This application is related to co-pending U.S. patent application Ser.No. 12/253,051 filed Oct. 16, 2008.

This application is related to co-pending U.S. patent application Ser.No. 12/190,449 filed Aug. 12, 2008.

This application is related to co-pending U.S. patent application Ser.No. 12/187,477 filed Aug. 7, 2008.

This application is related to co-pending U.S. patent application Ser.No. 12/218,558 and U.S. patent application Ser. No. 12/218,582 filedJul. 16, 2008.

This application is related to co-pending U.S. patent application Ser.No. 12/123,864 filed May 20, 2008.

This application is related to co-pending U.S. patent application Ser.No. 12/102,550 filed Apr. 14, 2008.

This application is related to co-pending U.S. patent application Ser.No. 12/047,842, and U.S. Ser. No. 12/047,944, filed Mar. 13, 2008.

This application is related to co-pending U.S. patent application Ser.No. 12/023,772, filed Jan. 31, 2008.

This application is related to co-pending U.S. patent application Ser.No. 11/956,069, filed Dec. 13, 2007.

This application is also related to co-pending U.S. patent applicationSer. Nos. 11/860,142 and 11/860,183 filed Sep. 24, 2007.

This application is also related to co-pending U.S. patent applicationSer. No. 11/836,402 filed Aug. 8, 2007.

This application is also related to co-pending U.S. patent applicationSer. No. 11/616,596 filed Dec. 27, 2006.

This application is also related to co-pending U.S. patent applicationSer. No. 11/614,332 filed Dec. 21, 2006.

This application is also related to co-pending U.S. patent applicationSer. No. 11/445,793 filed Jun. 2, 2006.

This application is also related to co-pending U.S. patent applicationSer. No. 11/500,053 filed Aug. 7, 2006.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of semiconductor devices, andto fabrication processes and devices such as multijunction solar cellsbased on III-V semiconductor compounds including a metamorphic layer.Such devices are also known as inverted metamorphic multijunction solarcells.

2. Description of the Related Art

Solar power from photovoltaic cells, also called solar cells, has beenpredominantly provided by silicon semiconductor technology. In the pastseveral years, however, high-volume manufacturing of III-V compoundsemiconductor multijunction solar cells for space applications hasaccelerated the development of such technology not only for use in spacebut also for terrestrial solar power applications. Compared to silicon,III-V compound semiconductor multijunction devices have greater energyconversion efficiencies and generally more radiation resistance,although they tend to be more complex to manufacture. Typical commercialIII-V compound semiconductor multijunction solar cells have energyefficiencies that exceed 27% under one sun, air mass 0 (AM0),illumination, whereas even the most efficient silicon technologiesgenerally reach only about 18% efficiency under comparable conditions.Under high solar concentration (e.g., 500×), commercially availableIII-V compound semiconductor multijunction solar cells in terrestrialapplications (at AM1.5D) have energy efficiencies that exceed 37%. Thehigher conversion efficiency of III-V compound semiconductor solar cellscompared to silicon solar cells is in part based on the ability toachieve spectral splitting of the incident radiation through the use ofa plurality of photovoltaic regions with different band gap energies,and accumulating the current from each of the regions.

Typical III-V compound semiconductor solar cells are fabricated on asemiconductor wafer in vertical, multijunction structures. Theindividual solar cells or wafers are then disposed in horizontal arrays,with the individual solar cells connected together in an electricalseries circuit. The shape and structure of an array, as well as thenumber of cells it contains, are determined in part by the desiredoutput voltage and current.

In satellite and other space related applications, the size, mass andcost of a satellite power system are dependent on the power and energyconversion efficiency of the solar cells used. Putting it another way,the size of the payload and the availability of on-board services areproportional to the amount of power provided. Thus, as the payloadsbecome more sophisticated and consume more power, the efficiency andmass of the solar cells, which act as the power conversion devices forthe on-board power systems, become increasingly more important.

Inverted metamorphic solar cell structures such as described in M. W.Wanlass et al., Lattice Mismatched Approaches for High Performance,III-V Photovoltaic Energy Converters (Conference Proceedings of the31^(st) IEEE Photovoltaic Specialists Conference, Jan. 3-7, 2005, IEEEPress, 2005) present an important conceptual starting point for thedevelopment of future commercial high efficiency solar cells. Thestructures described in such reference present a number of practicaldifficulties relating to the appropriate choice of materials andfabrication steps, for a number of different layers of the cell.

Prior to the inventions described in this and the related applicationsnoted above, the materials and fabrication steps disclosed in the priorart have not been adequate to produce a commercially viable and energyefficient inverted metamorphic multijunction solar cell usingcommercially established fabrication processes.

SUMMARY OF THE INVENTION

Briefly, and in general terms, the present invention provides a methodof manufacturing a solar cell, by providing a gallium arsenide carrierwith a prepared bonding surface; providing a support substrate; bondingthe gallium arsenide carrier and the support substrate to produce acomposite structure; detaching the bulk of the gallium arsenide carrierfrom the composite structure, leaving a gallium arsenide substrate onthe support substrate; and depositing a sequence of layers ofsemiconductor material forming a solar cell on the gallium arsenidesubstrate.

In another aspect, the present invention provides a method ofmanufacturing a solar cell, by providing a germanium carrier with aprepared bonding surface; providing a support substrate; bonding thegermanium carrier and the support substrate to produce a compositestructure; detaching the bulk of the germanium carrier from thecomposite structure, leaving a germanium substrate on the sapphiresubstrate; and depositing a sequence of layers of semiconductor materialforming a solar cell on the germanium substrate.

In another aspect, the present invention further provides subsequentlypreparing a new bonding surface on the detached bulk portion of thegallium arsenide or germanium carrier to form a new carrier; providing anew support substrate; bonding the new gallium arsenide or germaniumcarrier and the new support substrate to produce a new compositestructure; detaching the bulk of the new gallium arsenide or germaniumcarrier from the new composite structure, leaving a new gallium arsenideor germanium growth substrate on the new support substrate; anddepositing a sequence of layers of semiconductor material forming asolar cell on the new gallium arsenide or germanium growth substrate.

In another aspect, the present invention further provides subsequentlymounting a surrogate second substrate on top of the sequence of layersof semiconductor material forming a solar cell; and removing the galliumarsenide or germanium growth substrate.

In another aspect, the present invention provides that depositing thesequence of layers of semiconductor material forming a solar cellincludes forming a first subcell on the growth substrate comprising afirst semiconductor material with a first band gap and a first latticeconstant; forming a second subcell comprising a second semiconductormaterial with a second band gap and a second lattice constant, whereinthe second band gap is less than the first band gap and the secondlattice constant is greater than the first lattice constant; forming alattice constant transition material positioned between the firstsubcell and the second subcell, said lattice constant transitionmaterial having a lattice constant that changes gradually from the firstlattice constant to the second lattice constant.

In still another aspect, the present invention provides a method ofmanufacturing a solar cell by providing a gallium arsenide carrier witha prepared bonding surface; providing a support substrate; bonding thegallium arsenide carrier and the support substrate to produce acomposite structure; detaching the bulk of the gallium arsenide carrierfrom the composite structure, leaving a gallium arsenide substrate onthe support substrate; forming a first solar subcell having a first bandgap on the gallium arsenide substrate; forming a second solar subcelldisposed over the first solar subcell having a second band gap smallerthan the first band gap; forming a graded interlayer disposed over thesecond subcell having a third band gap greater than the second band gap;forming a third solar subcell disposed over the graded interlayer havinga fourth band gap smaller than the second band gap and latticemismatched with respect to the second subcell; and forming a fourthsolar subcell disposed over said third subcell having a fifth band gapsmaller than said fourth band gap and lattice matched with respect tosaid third subcell.

Not all of these aspects or features of the present invention needactually be implemented in any one embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be better and more fully appreciated by reference tothe following detailed description when considered in conjunction withthe accompanying drawings, wherein:

FIG. 1A is a cross-sectional view of the support substrate of thepresent invention;

FIG. 1B is a cross-sectional view of the carrier substrate of thepresent invention after surface preparation;

FIG. 1C is a cross-sectional view of the composite structure resultingfrom the bonding of the support and carrier substrates;

FIG. 1D is a cross-sectional view of the composite structure of FIG. 1Cafter removal of the bulk of the carrier substrate;

FIG. 2A is a perspective view of a polyhedral representation of asemiconductor lattice structure showing the crystal planes;

FIG. 2B is a perspective view of the GaAs crystal lattice showing theposition of the gallium and arsenic atoms;

FIG. 3A is a perspective view of the plane P of the substrate employedin the present invention superimposed over the crystal diagram of FIG.2A;

FIG. 3B is a graphical depiction of the surface of the plane of thesubstrate employed in the present invention;

FIG. 4A is a graph representing the band gap of certain binary materialsand their lattice constants and a range of materials utilized in aninverted metamorphic multijunction (IMM) solar cell in the prior art;

FIG. 4B is a graph representing the band gap of certain binary materialsand their lattice constants and a range of materials utilized in aninverted metamorphic multijunction (IMM) solar cell according to thepresent invention;

FIG. 5 is a diagram representing the range of band gaps of variousGaInAlAs materials as a function of the relative concentration of Al,In, and Ga;

FIG. 6 is a graph representing the Ga mole fraction versus the Al to Inmole fraction in GaInAlAs materials that is necessary to achieve aconstant 1.5 eV band gap;

FIG. 7 is a graph representing the mole fraction versus lattice constantin GaInAlAs materials that is necessary to achieve a constant 1.5 eVband gap;

FIG. 8 is a cross-sectional view of the solar cell of the inventionafter the deposition of semiconductor layers on the growth substrate;

FIG. 9 is a cross-sectional view of the solar cell of FIG. 8 after thenext sequence of process steps;

FIG. 10 is a cross-sectional view of the solar cell of FIG. 9 after thenext sequence of process steps;

FIG. 11 is a cross-sectional view of the solar cell of FIG. 10 after thenext sequence of process steps;

FIG. 12 is a cross-sectional view of the solar cell of FIG. 11 after thenext process step in which a surrogate substrate is attached;

FIG. 13A is a cross-sectional view of the solar cell of FIG. 12 afterthe next process step in which the original substrate is removed;

FIG. 13B is another cross-sectional view of the solar cell of FIG. 13Awith an orientation depicting the surrogate substrate at the bottom ofthe Figure;

FIG. 14 is a highly simplified cross-sectional view of the solar cell ofFIG. 13B;

FIG. 15 is a cross-sectional view of the solar cell of FIG. 14 after thenext process step;

FIG. 16 is a cross-sectional view of the solar cell of FIG. 15 after thenext process step in which the grid lines are formed over the contactlayer;

FIG. 17 is a cross-sectional view of the solar cell of FIG. 16 after thenext process step;

FIG. 18A is a top plan view of a wafer in which four solar cells arefabricated;

FIG. 18B is a bottom plan view of a wafer of FIG. 18A;

FIG. 18C is a top plan view of a wafer in which two solar cells arefabricated;

FIG. 19 is a cross-sectional view of the solar cell of FIG. 17 after thenext process step;

FIG. 20A is a cross-sectional view of the solar cell of FIG. 19 afterthe next process step;

FIG. 20B is a cross-sectional view of the solar cell of FIG. 20A afterthe next process step;

FIG. 21 is a top plan view of the wafer of FIG. 20B depicting thesurface view of the trench etched around the cell;

FIG. 22A is a cross-sectional view of the solar cell of FIG. 20B afterthe next process step in a first embodiment of the present invention;

FIG. 22B is a cross-sectional view of the solar cell of FIG. 22A afterthe next process step in a second embodiment of the present invention;

FIG. 22C is a cross-sectional view of the solar cell of FIG. 22A afterthe next process step in a third embodiment of the present invention inwhich a cover glass is attached;

FIG. 23 is a cross-sectional view of the solar cell of FIG. 22C afterthe next process step in a third embodiment of the present invention inwhich the surrogate substrate is removed; and

FIG. 24 is a graph of the doping profile in a base and adjoining emitterlayer in the metamorphic solar cell according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Details of the present invention will now be described includingexemplary aspects and embodiments thereof. Referring to the drawings andthe following description, like reference numbers are used to identifylike or functionally similar elements, and are intended to illustratemajor features of exemplary embodiments in a highly simplifieddiagrammatic manner. Moreover, the drawings are not intended to depictevery feature of the actual embodiment nor the relative dimensions ofthe depicted elements, and are not drawn to scale.

The basic concept of fabricating an inverted metamorphic multijunction(IMM) solar cell is to grow the subcells of the solar cell on asubstrate in a “reverse” sequence. That is, the high band gap subcells(i.e. subcells with band gaps in the range of 1.8 to 2.1 eV), whichwould normally be the “top” subcells facing the solar radiation, aregrown epitaxially on a semiconductor growth substrate, such as forexample GaAs or Ge, and such subcells are therefore lattice matched tosuch substrate. One or more lower band gap middle subcells (i.e. withband gaps in the range of 1.2 to 1.8 eV) can then be grown on the highband gap subcells.

At least one lower subcell is formed over the middle subcell such thatthe at least one lower subcell is substantially lattice mismatched withrespect to the growth substrate and such that the at least one lowersubcell has a third lower band gap (i.e. a band gap in the range of 0.7to 1.2 eV). A surrogate substrate or support structure is provided overthe “bottom” or substantially lattice mismatched lower subcell, and thegrowth semiconductor substrate is subsequently removed. (The growthsubstrate may then subsequently be re-used for the growth of a secondand subsequent solar cells).

The lattice constants and electrical properties of the layers in thesemiconductor structure are preferably controlled by specification ofappropriate reactor growth temperatures and times, and by use ofappropriate chemical composition and dopants. The use of a vapordeposition method, such as Organo Metallic Vapor Phase Epitaxy (OMVPE),Metal Organic Chemical Vapor Deposition (MOCVD), Molecular Beam Epitaxy(MBE), or other vapor deposition methods for the reverse growth mayenable the layers in the monolithic semiconductor structure forming thecell to be grown with the required thickness, elemental composition,dopant concentration and grading and conductivity type.

A variety of different features of inverted metamorphic multijunctionsolar cells are disclosed in the related applications noted above. Thepresent invention is directed to an alternative growth and processtechnology for the epitaxial fabrication of the semiconductor solar celllayers in a multijunction solar cell, and in particular in an invertedmetamorphic multijunction solar cell. In the preferred embodiment to bedescribed, the epitaxial layers of the IMM solar cell are grown on arelative thin semiconductor structure which consists of a GaAs or Gegrowth template (or other suitable material) attached to a sapphire orsapphire/spinal substrate or support. The sapphire/spinal substrate canbe designed or specified and selected to have a coefficient of thermalexpansion (CTE) that matches that of relevant III/V compounds such asGaAs, GaInPa, etc. used in the solar cell fabrication.

According to the embodiments described herein, the thin gallium arsenidegrowth template is formed by bonding a gallium arsenide wafer to asapphire substrate and detaching the bulk of the gallium arsenide wafer,leaving a thin layer of gallium arsenide on the sapphire substrate. Thebulk of the gallium arsenide carrier is detached in such a way that itis not destroyed and can be reused to form additional solar cells onother sapphire substrates. Reusing gallium arsenide carriers in this wayto form additional solar cells significantly reduces the per-unit costof gallium arsenide-based solar cells.

The IMM cell structure is grown on the growth template mentioned aboveby MOCVD or equivalent growth technology. After growth, the structure isprocessed. During processing, a release technology is used to remove thesapphire or sapphire/spinal substrate. The sapphire or sapphire/spinalsubstrate can be reused by attaching another GaAs, Ge (or other)substrate for forming additional solar cells.

The release of the sapphire (or sapphire/spiral) substrate can be donethrough wet etching or through a layer release process. The wet etchingwould laterally etch a layer, relaxing the growth substrate and thelaser retrace process would melt a layer and accomplish the same kind ofrelease of the growth substrate.

The value of the proposed process is that the grinding and etching ofthe growth template no longer needs to be done. The main part of thegrowth template i.e., the sapphire/spinal substrate or support, is alsonow reusable. Much less GaAs or Ge material is also necessary, justenough of a layer to provide a growth template.

A second advantage of this approach is that different lattice constantscan now be used instead of only GaAs or Ge. If a smaller latticeconstant than GaAs (or Ge) can be used, then a higher band gap topsubcell can now be incorporated into the solar cell versus the use of aGaInP₂ subcell (with band gap around 1.90 eV) that is now being used incurrently available IMM solar cell structures.

FIGS. 1A-1D are cross-sectional views of a sapphire substrate 40 and agallium arsenide carrier 50 during different steps of bonding thecarrier 50 to the substrate 40, removing a bulk of the carrier 50 afterbonding and forming a solar cell on the remaining gallium arsenide layer51 bonded to the sapphire substrate 40. FIG. 1A shows the sapphiresubstrate 40. FIG. 1B shows the gallium arsenide carrier 50. The carrier50 includes the thin gallium arsenide layer 51 adjacent a bulk region 52of gallium arsenide.

According to one embodiment, the gallium arsenide layer 51 is formed byimplanting a species such as hydrogen ions and/or rare gases into thegallium arsenide carrier 50 to form a defect layer in the galliumarsenide carrier. Any known process for implanting species such ashydrogen ions and/or rare gases into a semiconductor wafer can be used.For example, the gallium arsenide layer 51 can be formed in the carrier50 in accordance with any of the species implantation techniquesdisclosed in U.S. Pat. Nos. 7,288,430, 7,235,462, 6,946,317 and6,794,276, each assigned to S.O.I. Tec Silicon on Insulator Technologiesand the contents of which are herein incorporated by reference in theirentirety, respectively. The dose and/or energy of the implanted speciescan be adjusted so that a peak concentration of the implanted species isformed at a certain depth in the carrier 50, thereby weakening thegallium arsenide layer 51 due to the ion implantation at or near thisdepth. The bulk region 52 of the gallium arsenide carrier 50 is notweakened during the implantation process.

In one embodiment, the gallium arsenide carrier 50 has a preparedbonding surface which can be roughened prior to bonding to the sapphiresubstrate 40 as illustrated by the exploded view shown in FIG. 1B. Theprepared bonding surface of the carrier 50 can be roughened using anysuitable chemical or mechanical roughening process. Roughening thesurface of the carrier 50 improves the bonding characteristics of thecarrier 50.

FIG. 1C shows the gallium arsenide carrier 50 and the sapphire substrate40 after they are bonded together. According to an embodiment, theprepared bonding surface of the gallium arsenide carrier 50 is directlymolecularly bonded to a surface of the sapphire substrate 40, e.g.,under elevated temperature and pressure. A thin bonding layer betweenthe layer 51 and the sapphire substrate 40 is not shown in the Figuresin order to simplify the drawings. According to one embodiment, theweakened layer 51 of gallium arsenide formed by the implantation ofspecies such as hydrogen ions and/or rare gases into the carrier 50 isbonded to the sapphire substrate 40. The bulk 52 of the gallium arsenidecarrier 50 is then detached from the composite structure, leaving thethin layer 51 of gallium arsenide on the sapphire substrate 40.

In one embodiment, the bulk 52 of the gallium arsenide carrier 50 isdetached from the sapphire substrate 40 by annealing the carrier 50 in ahot environment such as a furnace or any equipment for rapid thermalannealing. The effect of annealing temperature and time further weakensthe carrier 50 at the thin gallium arsenide layer 51 introduced byatomic implantation which leads to detaching. By detaching along thisregion during or after annealing, the thin layer 51 of gallium arsenideremains bonded to the sapphire substrate 40 as shown in FIG. 1D. Thedetached bulk portion 52 of the carrier 50 is not destroyed, and thuscan be reused.

According to one embodiment, the thin gallium arsenide layer 51 bondedto the sapphire substrate 40 has a thickness of about 5 μm and the bulk52 of the carrier 50 detached from the composite structure has athickness of about 395 μm. The thin layer 51 of gallium arsenide bondedto the sapphire substrate 40 acts as a substrate on which a solar cellcan be formed. In one embodiment, the gallium arsenide layer 51 isprepared or smoothed before a solar cell is formed on the layer 51.Smoothing or surface preparation can be performed using any suitabletechnique such as chemical-mechanical polishing, etching by gas cluster,ion beam or reactive ion etching, HCL-smoothing, etc. Hereinafter inthis application, the thin GaAs layer 51 on the sapphire support 40 willsimply be referred to as the “substrate.”

As mentioned above, the bulk 52 of the gallium arsenide carrier 50detached from the sapphire substrate 40 can be reused. In oneembodiment, the bulk 52 of the gallium arsenide carrier 50 is reused toform a new solar cell on a new sapphire substrate (not shown) asdescribed above. That is, a new bonding surface is prepared on thedetached bulk portion 52 of the gallium arsenide carrier 50 to form anew gallium arsenide carrier. The new gallium arsenide carrier is bondedto a new sapphire substrate to produce a new composite structure. Thebulk of the new gallium arsenide carrier is detached from the newcomposite structure as described above, leaving a new gallium arsenidesubstrate on the new sapphire substrate. A new sequence of layers ofsemiconductor material can then be deposited on the new gallium arsenidesubstrate to form a new solar cell.

The gallium arsenide carrier 50 (as well as the gallium arsenide growthlayer or template 51) is preferably an off-cut substrate, as will bemore particularly explained with reference to FIGS. 2A through FIG. 3Bthat follow. FIG. 2A is a perspective view of a polyhedralrepresentation of a semiconductor lattice structure showing the crystalplanes. The Miller indices are used to identify the planes, and thecrystal structure is represented in the Figure by a truncated cube withthe (001) plane at the top. In the case of a GaAs compoundsemiconductor, which is the material of interest in the presentinvention, the crystal structure is known as the zinc blended structure,and is shown in FIG. 2B, which represents a combination of twointerpenetrating face centered cubic sublattices. The lattice constant(i.e., the distance between the arsenic atoms in the crystal) is 0.565nm.

FIG. 2B is a perspective view of the GaAs crystal lattice showing theposition of the gallium and arsenic atoms, with the corresponding Millerindices identifying the lattice planes.

FIG. 3A is a perspective view of the plane P of the substrate surfaceemployed in the present invention superimposed over the crystal diagramof FIG. 2A. The plane P is seen to pivot from a point on the (001) plane(in this representation, the rear corner of the top surface of thepolyhedron) in the direction of the (111) plane, or more accurately the(111)A plane, where the letter “A” refers to the plane formed by thesublattice of arsenic atoms. The angle of pivot according to the presentinvention defines the angle of off-cut of the substrate defined from the(001) plane by the plane P, which is at least 6° and preferablyapproximately 15°.

Although the present invention ideally provides for an offcut in the(111)A direction, it may be that during production and fabrication ofvarious wafer lots, the alignment or cutting process is not as preciseor exacting as may be specified by the present invention, and theresulting plane P may pivot slightly in the direction of the adjacent(011) or (101) planes, as well as in the direction of the (111)A plane.Such deviations, whether inadvertent or for some other mechanical orstructural reason, are contemplated to be within the scope of thepresent invention as well.

Thus, in the most general form, as used in the present disclosure therecitation “off-cut from the (001) crystal plane by at least 6° towardsthe (111)A plane” contemplates and includes the off-cut plane P pivotingtowards any of the following planes:

(i) an adjacent (111)A plane by at least 6 degrees and at most 20degrees;

(ii) an adjacent (011) plane by at most approximately one degree;

(iii) an adjacent (101) plane by at most approximately one degree; and

(iv) any plane lying in the continuum of planes between (i) and (ii),(i) and (iii), or

(ii) and (iii) above.

FIG. 3B is an enlarged perspective view of an off-cut GaAs substrateshowing how the off-cut results in a staircase of planar steps extendingover the surface of the substrate.

FIG. 4A is a graph representing the band gap of certain binary materialsand their lattice constants. The band gap and lattice constants ofternary materials are located on the lines drawn between typicalassociated binary materials (such as the ternary material GaAlAs beinglocated between the GaAs and AlAs points on the graph, with the band gapof the ternary material lying between 1.42 eV for GaAs and 2.16 eV forAlAs depending upon the relative amount of the individual constituents).Thus, depending upon the desired band gap, the material constituents ofternary materials can be appropriately selected for growth. The line Adrawn on the graph represents one of the material combinations of bandgaps and lattice constants of ternary materials that can be grown on agallium arsenide substrate as is known in the prior art.

FIG. 4B is a graph representing the band gap of certain binary materialsand their lattice constants as shown in FIG. 4A, with the line Brepresenting one of the material combinations of band gaps and latticeconstants of ternary materials that can be grown on an alternatesubstrate according to the present invention. Thus, depending upon thedesired band gap, the material constituents of the growth template andthe ternary materials that can be lattice matched to it can beappropriately selected for design of new solar cell subcell sequences.

FIG. 5 is a diagram representing the range of band gaps of variousGaInAlAs materials as a function of the relative concentration of Al,In, and Ga. This diagram illustrates how the selection of a constantband gap sequence of layers of GaInAlAs used in the metamorphic layermay be designed through the appropriate selection of the relativeconcentration of Al, In, and Ga to meet the different lattice constantrequirements for each successive layer. Thus, whether 1.5 eV or 1.1 eVor other band gap value is the desired constant band gap, the diagramillustrates a continuous curve for each band gap, representing theincremental changes in constituent proportions as the lattice constantchanges, in order for the layer to have the required band gap andlattice constant.

FIG. 6 is a graph that further illustrates the selection of a constantband gap sequence of layers of GaInAlAs used in the metamorphic layer byrepresenting the Ga mole fraction versus the Al to In mole fraction inGaInAlAs materials that is necessary to achieve a constant 1.5 eV bandgap.

FIG. 7 is a graph that further illustrates the selection of a constantband gap sequence of layers of GaInAlAs used in the metamorphic layer byrepresenting the mole fraction versus lattice constant in GaInAlAsmaterials that is necessary to achieve a constant 1.5 eV band gap.

FIG. 8 depicts a portion of the multijunction solar cell to befabricated according to the present invention after the sequentialformation of the three subcells A, B and C on a GaAs growth substrate.More particularly, there is shown a growth substrate 51 mounted over asupport 40, as derived from the process shown in FIGS. 1A through 1D.The growth substrate is preferably gallium arsenide (GaAs), but may alsobe germanium (Ge) or other suitable material. For GaAs, the substrate ispreferably a 15° off-cut substrate, that is to say, its surface isorientated 15° off the (100) plane towards the (111)A plane, as morefully described in U.S. patent application Ser. No. 12/047,944, filedMar. 13, 2008.

In the case of a Ge substrate, a nucleation layer (not shown) isdeposited directly on the substrate 51. On the substrate, or over thenucleation layer (in the case of a Ge substrate), a buffer layer 102 andan etch stop layer 103 are further deposited. In the case of GaAssubstrate, the buffer layer 102 is preferably GaAs. In the case of Gesubstrate, the buffer layer 102 is preferably InGaAs. A contact layer104 of GaAs is then deposited on layer 103, and a window layer 105 ofA1InP is deposited on the contact layer. The subcell A, consisting of ann+ emitter layer 106 and a p-type base layer 107, is then epitaxiallydeposited on the window layer 105. The subcell A is generally latticematched to the growth substrate 101.

It should be noted that the multijunction solar cell structure could beformed by any suitable combination of group III to V elements listed inthe periodic table subject to lattice constant and band gaprequirements, wherein the group III includes boron (B), aluminum (Al),gallium (Ga), indium (In), and thallium (T). The group IV includescarbon (C), silicon (Si), germanium (Ge), and tin (Sn). The group Vincludes nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb), andbismuth (Bi).

In the preferred embodiment, the emitter layer 106 is composed ofInGa(Al)P and the base layer 107 is composed of InGa(Al)P. The aluminumor Al term in parenthesis in the preceding formula means that Al is anoptional constituent, and in this instance may be used in an amountranging from 0% to 30%. The doping profile of the emitter and baselayers 106 and 107 according to the present invention will be discussedin conjunction with FIG. 23.

Subcell A will ultimately become the “top” subcell of the invertedmetamorphic structure after completion of the process steps according tothe present invention to be described hereinafter.

On top of the base layer 107 a back surface field (“BSF”) layer 108 isdeposited and used to reduce recombination loss, preferably p+ AlGaInP.

The BSF layer 108 drives minority carriers from the region near thebase/BSF interface surface to minimize the effect of recombination loss.In other words, the BSF layer 108 reduces recombination loss at thebackside of the solar subcell A and thereby reduces the recombination inthe base.

On top of the BSF layer 108 is deposited a sequence of heavily dopedp-type and n-type layers 109 which forms a tunnel diode which is anohmic circuit element to connect subcell A to subcell B. These layersare preferably composed of p++ AlGaAs, and n++ InGaP.

On top of the tunnel diode layers 109 a window layer 110 is deposited,preferably n+ InAlP. The window layer 110 used in the subcell B operatesto reduce the interface recombination loss. It should be apparent to oneskilled in the art, that additional layer(s) may be added or deleted inthe cell structure without departing from the scope of the presentinvention.

On top of the window layer 110 the layers of subcell B are deposited:the n-type emitter layer 111 and the p-type base layer 112. These layersare preferably composed of InGaP and In_(0.015)GaAs respectively (for aGe substrate or growth template), or InGaP and GaAs respectively (for aGaAs substrate), although any other suitable materials consistent withlattice constant and band gap requirements may be used as well. Thus,subcell B may be composed of a GaAs, GaInP, GaInAs, GaAsSb, or GaInAsNemitter region and a GaAs, GaInAs, GaAsSb, or GaInAsN base region. Thedoping profile of layers 111 and 112 according to the present inventionwill be discussed in conjunction with FIG. 23.

In the preferred embodiment of the present invention, the middle subcellemitter has a band gap equal to the top subcell emitter, and the bottomsubcell emitter has a band gap greater than the band gap of the base ofthe middle subcell. Therefore, after fabrication of the solar cell, andimplementation and operation, neither the middle subcell B nor thebottom subcell C emitters will be exposed to absorbable radiation.Substantially radiation will be absorbed in the bases of cells B and C,which have narrower band gaps than the emitters. Therefore, theadvantages of using heterojunction subcells are: (i) the shortwavelength response for both subcells will improve, and (ii) the bulk ofthe radiation is more effectively absorbed and collected in the narrowerband gap base. The effect will be to increase J_(sc).

On top of the cell B is deposited a BSF layer 113 which performs thesame function as the BSF layer 109. A p++/n++ tunnel diode 114 isdeposited over the BSF layer 113 similar to the layers 109, againforming an ohmic circuit element to connect subcell B to subcell C.These layers 114 are preferably compound of p++ AlGaAs and n++ InGaP.

A barrier layer 115, preferably composed of n-type InGa(Al)P, isdeposited over the tunnel diode 114, to a thickness of about 1.0 micron.Such barrier layer is intended to prevent threading dislocations frompropagating, either opposite to the direction of growth into the middleand top subcells A and B, or in the direction of growth into the bottomsubcell C, and is more particularly described in copending U.S. patentapplication Ser. No. 11/860,183, filed Sep. 24, 2007.

A metamorphic layer (or graded interlayer) 116 is deposited over thebarrier layer 115 using a surfactant, Layer 116 is preferably acompositionally step-graded series of InGaAlAs layers, preferably withmonotonically changing lattice constant, so as to achieve a gradualtransition in lattice constant in the semiconductor structure fromsubcell B to subcell C while minimizing threading dislocations fromoccurring. The band gap of layer 116 is constant throughout itsthickness preferably approximately 1.5 eV or otherwise consistent with avalue slightly greater than the base band gap of the middle subcell B.The preferred embodiment of the graded interlayer may also be expressedas being composed of (In_(x)Ga_(1-x))_(y) A1_(y-1)As, with x and yselected such that the band gap of the interlayer remains constant atapproximately 1.50 eV.

In the surfactant assisted growth of the metamorphic layer 116, asuitable chemical element is introduced into the reactor during thegrowth of layer 116 to improve the surface characteristics of the layer.In the preferred embodiment, such element may be a dopant or donor atomsuch as selenium (Se) or tellurium (Te). Small amounts of Se or Te aretherefore incorporated in the metamorphic layer 116, and remain in thefinished solar cell. Although Se or Te are the preferred n-type dopantatoms, other non-isoelectronic surfactants may be used as well.

Surfactant assisted growth results in a much smoother or planarizedsurface. Since the surface topography affects the bulk properties of thesemiconductor material as it grows and the layer becomes thicker, theuse of the surfactants minimizes threading dislocations in the activeregions, and therefore improves overall solar cell efficiency.

As an alternative to the use of non-isoelectronic surfactants one mayuse an isoelectronic surfactant. The term “isoelectronic” refers tosurfactants such as antimony (Sb) or bismuth (Bi), since such elementshave the same number of valence electrons as the P atom of InGaP, or theAs atom in InGaAlAs, in the metamorphic buffer layer. Such Sb or Bisurfactants will not typically be incorporated into the metamorphiclayer 116.

In an alternative embodiment where the solar cell has only two subcells,and the “middle” cell B is the uppermost or top subcell in the finalsolar cell, wherein the “top” subcell A would typically have a band gapof 1.8 to 1.9 eV, then the band gap of the interlayer would remainconstant at 1.9 eV.

In the inverted metamorphic structure described in the Wanlass et al.paper cited above, the metamorphic layer consists of ninecompositionally graded InGaP steps, with each step layer having athickness of 0.25 micron. As a result, each layer of Wanlass et al. hasa different band gap. In the preferred embodiment of the presentinvention, the layer 116 is composed of a plurality of layers ofInGaAlAs, with monotonically changing lattice constant, each layerhaving the same band gap, approximately 1.5 eV.

The advantage of utilizing a constant band gap material such as InGaA1Asis that arsenide-based semiconductor material is much easier to processin standard commercial MOCVD reactors, while the small amount ofaluminum assures radiation transparency of the metamorphic layers.

Although the preferred embodiment of the present invention utilizes aplurality of layers of InGaA1As for the metamorphic layer 116 forreasons of manufacturability and radiation transparency, otherembodiments of the present invention may utilize different materialsystems to achieve a change in lattice constant from subcell B tosubcell C. Thus, the system of Wanlass using compositionally gradedInGaP is a further embodiment of the present invention. Otherembodiments of the present invention may utilize continuously graded, asopposed to step graded, materials. More generally, the graded interlayermay be composed of any of the As, P, N, Sb based III-V compoundsemiconductors subject to the constraints of having the in-plane latticeparameter greater or equal to that of the second solar cell and lessthan or equal to that of the third solar cell, and having a band gapenergy greater than that of the second solar cell.

In another embodiment of the present invention, an optional secondbarrier layer 117 may be deposited over the InGaAlAs metamorphic layer116. The second barrier layer 117 will typically have a differentcomposition than that of barrier layer 115, and performs essentially thesame function of preventing threading dislocations from propagating. Inthe preferred embodiment, barrier layer 117 is n+ type GaInP.

A window layer 118 preferably composed of n+ type GaInP is thendeposited over the barrier layer 117 (or directly over layer 116, in theabsence of a second barrier layer). This window layer operates to reducethe recombination loss in subcell “C”. It should be apparent to oneskilled in the art that additional layers may be added or deleted in thecell structure without departing from the scope of the presentinvention.

On top of the window layer 118, the layers of cell C are deposited: then+ emitter layer 119, and the p-type base layer 120. These layers arepreferably composed of n type InGaAs and p type InGaAsP respectively, orn type InGaP and p type InGaAs for a heterojunction subcell, althoughanother suitable materials consistent with lattice constant and band gaprequirements may be used as well. The doping profile of layers 119 and120 will be discussed in connection with FIG. 23.

A BSF layer 121, preferably composed of p+ GaInP, is then deposited ontop of the cell C, the BSF layer performing the same function as the BSFlayers 108 and 113.

Next, a tunnel diode with layers 122 and 123 is deposited over the BSFlayer 121 similar to the layers 114 and 109, again forming an ohmiccircuit element to connect subcell C to subcell D. The p++ layer 122 ispreferably composed of GaInAsP, and the n++ layer 123 is preferablycomposed of GaInAsP.

In FIG. 9, a window layer 124 preferably composed of n type GaInAsP isthen deposited over the tunnel diode layer 123. This window layeroperates to reduce the recombination loss in subcell “D”. It should beapparent to one skilled in the art that additional layers may be addedor deleted in the cell structure without departing from the scope of thepresent invention.

On top of the window layer 124, the layers of cell D are deposited: then+ emitter layer 125, and the p-type base layer 126. These layers arepreferably composed of n type GaInAs and p type GaInAs respectively, orn type InGaP and p type InGaAs for a heterojunction subcell, althoughanother suitable materials consistent with lattice constant and band gaprequirements may be used as well. The doping profile of layers 125 and126 will be discussed in connection with FIG. 23.

Next, as shown in FIG. 10, a BSF layer 127, preferably composed of p+GaInAsP, is then deposited on top of the cell D, the BSF layerperforming the same function as the BSF layers 108, 113 and 121.

Finally, a p+ contact layer 128, preferably composed of p+ GaInAs isdeposited on the BSF layer 127.

In the next process step, a metal contact layer 129 is deposited overthe p+ semiconductor contact layer 128. The metal is preferably thesequence of metal layers Ti/Au/Ag/Au, although other suitable materialsand sequences can be used as well.

Also, the metal contact materials and layers are chosen so that it has aplanar interface with the underlying semiconductor contact layer, afterheat treatment to activate the ohmic contact. This is done so that (i) adielectric layer separating the metal from the semiconductor doesn'thave to be deposited and selectively etched in the metal contact areas;and (ii) the contact layer is specularly reflective over the wavelengthrange of interest.

FIG. 12 is a cross-sectional view of the solar cell of FIG. 11 after thenext process step in which a bonding layer 130 is deposited over themetal layer 129. In one embodiment of the present invention, the bondinglayer is an adhesive, preferably Wafer Bond (manufactured by BrewerScience, Inc. of Rolla, Mo.). In other embodiments of the presentinvention, a solder or eutectic bonding layer 130, such as described inU.S. patent application Ser. No. 12/271,127 filed Nov. 14, 2008, or abonding layer 130 such as described in U.S. patent application Ser. No.12/265,113 filed Nov. 5, 2008, may be used, where the surrogatesubstrate remains a permanent supporting component of the finished solarcell.

FIG. 13A is a cross-sectional view of the solar cell of FIG. 12 afterthe next process step in which a surrogate substrate 150, preferablysapphire, is attached. Alternatively, the surrogate substrate may beGaAs, Ge or Si, or other suitable material. The surrogate substrate isabout 40 mils in thickness, and in the case of embodiments in which thesurrogate substrate is to be removed, it is perforated with holes about1 mm in diameter, spaced 4 mm apart, to aid in subsequent removal of theadhesive and the substrate.

In the next process step, also depicted in FIG. 13A, the original growthsubstrate 51 and support 40 are removed by localized heating with alaser, and subsequent etching to remove layers 51 and 102.

FIG. 13B is a cross-sectional view of the solar cell of FIG. 13A withthe orientation with the surrogate substrate 150 being at the bottom ofthe Figure. Subsequent Figures in this application will assume suchorientation.

FIG. 14 is a simplified cross-sectional view of the solar cell of FIG.13B depicting just a few of the top layers and lower layers over thesurrogate substrate 150, after the removal of the buffer layer 102.

FIG. 15 is a cross-sectional view of the solar cell of FIG. 14 after thenext process step in which the etch stop layer 103 is removed by aHCl/H₂O solution.

FIG. 16 is a cross-sectional view of the solar cell of FIG. 15 after thenext sequence of process steps in which a photoresist mask (not shown)is placed over the contact layer 104 to form the grid lines 501. As willbe described in greater detail below, the grid lines 501 are depositedvia evaporation and lithographically patterned and deposited over thecontact layer 104. The mask is subsequently lifted off to form thefinished metal grid lines 501 as depicted in subsequent Figures.

As more fully described in U.S. patent application Ser. No. 12/218,582filed Jul. 18, 2008, hereby incorporated by reference, the grid lines501 are preferably composed of Pd/Ge/Ti/Pd/Au, although other suitablematerials may be used as well.

FIG. 17 is a cross-sectional view of the solar cell of FIG. 16 after thenext process step in which the grid lines are used as a mask to etchdown the surface to the window layer 105 using a citric acid/peroxideetching mixture.

FIG. 18A is a top plan view of a wafer in which four solar cells areimplemented. The depiction of four cells is for illustration purposesonly, and the present invention is not limited to any specific number ofcells per wafer.

In each cell there are grid lines 501 (more particularly shown incross-section in FIG. 17), an interconnecting bus line 502, and acontact pad 503. The geometry and number of grid and bus lines and thecontact pad are illustrative and the present invention is not limited tothe illustrated embodiment.

FIG. 18B is a bottom plan view of the wafer with four solar cells shownin FIG. 18A.

FIG. 18C is a top plan view of a wafer in which two solar cells areimplemented. The depiction of the two cells in this Figure is forillustration purposes only.

FIG. 19 is a cross-sectional view of the solar cell of FIG. 17 after thenext process step in which an antireflective (ARC) dielectric coatinglayer 130 is applied over the entire surface of the “bottom” side of thewafer with the grid lines 501.

FIG. 20A is a cross-sectional view of the solar cell of FIG. 19 afterthe next process step according to the present invention in which firstand second annular channels 510 and 511, or portion of the semiconductorstructure are etched down to the metal layer 129 using phosphide andarsenide etchants. These channels define a peripheral boundary betweenthe cell and the rest of the wafer, and leave a mesa structure whichconstitutes the solar cell. The cross-section depicted in FIG. 20A isthat as seen from the A-A plane shown in FIG. 21. In a preferredembodiment, channel 510 is substantially wider than that of channel 511.

FIG. 20B is a cross-sectional view of the solar cell of FIG. 20A afterthe next process step in which channel 511 is exposed to a metaletchant, layer 123 in the channel 511 is removed, and channel 511 isextended in depth approximately to the top surface of the bond oradhesive layer 130.

FIG. 21 is a top plan view of the wafer of FIGS. 20A and 20B depictingthe channels 510 and 511 etched around the periphery of each cell.

FIG. 22A is a cross-sectional view of the solar cell of FIG. 20B afterthe individual solar cells (cell 1, cell 2, etc. shown in FIG. 21) arecut or scribed from the wafer through the channel 511, leaving avertical edge 515 extending through the surrogate substrate 150 at thelocation of the channel 511. In this first embodiment of the presentinvention, the surrogate substrate 150 forms the support for the solarcell in applications where a cover glass (such as provided in the thirdembodiment to be described below) is not required. In such anembodiment, electrical contact to the metal contact layer 129 may bemade through the channel 510.

FIG. 22B is a cross-sectional view of the solar cell of FIG. 22A afterthe next process step in a second embodiment of the present invention inwhich the surrogate substrate 150 is appropriately thinned to arelatively thin layer 150 a, by grinding, lapping, or etching. In thisembodiment, the thin layer 150 a forms the support for the solar cell inapplications where a cover glass, such as provided in the secondembodiment to be described below, is not required. In such anembodiment, electrical contact to the metal contact layer 129 may bemade through the channel 510.

FIG. 22C is a cross-sectional view of the solar cell of FIG. 22A afterthe next process step in a second embodiment of the present invention inwhich a cover glass 514 is secured to the top of the cell by an adhesive513. The cover glass 514 preferably covers the entire channel 510, butdoes not extend to channel 511. Although the use of a cover glass is thepreferred embodiment, it is not necessary for all implementations, andadditional layers or structures may also be utilized for providingadditional support or environmental protection to the solar cell.

FIG. 23 is a cross-sectional view of the solar cell of FIG. 22A afterthe next process step of the present invention in which the bond oradhesive layer 130, the surrogate substrate 150 and the peripheralportion 512 of the wafer is entirely removed, leaving only the solarcell with the cover glass 514 (or other layers or structures) on thetop, and the metal contact layer 129 on the bottom, which forms thebackside contact of the solar cell. The surrogate substrate 150 ispreferably removed by the use of the etchant ‘Wafer Bond Solvent’. Asnoted above, the surrogate substrate includes perforations over itssurface that allow the flow of etchant through the surrogate substrate150 to permit its lift off. After lift off, the surrogate substrate maybe reused in subsequent wafer processing operations.

FIG. 24 is a graph of a doping profile in the emitter and base layers inone or more subcells of the inverted metamorphic multijunction solarcell of the present invention. The various doping profiles within thescope of the present invention, and the advantages of such dopingprofiles are more particularly described in copending U.S. patentapplication Ser. No. 11/956,069 filed Dec. 13, 2007, herein incorporatedby reference. The doping profiles depicted herein are merelyillustrative, and other more complex profiles may be utilized as wouldbe apparent to those skilled in the art without departing from the scopeof the present invention.

It should be apparent to one skilled in the art, that additionallayer(s) may be added or deleted in the cell structure of FIG. 13Bwithout departing from the scope of the present invention.

It will be understood that each of the elements described above, or twoor more together, also may find a useful application in other types ofconstructions differing from the types of constructions described above.

Although the preferred embodiment of the present invention utilizes avertical stack of four subcells, the present invention can apply tostacks with fewer or greater number of subcells, i.e. two junctioncells, three junction cells, five junction cells, etc. as moreparticularly described in U.S. patent application Ser. No. 12/267,812filed Nov. 10, 2008. In the case of four or more junction cells, the useof more than one metamorphic grading interlayer may also be utilized, asmore particularly described in U.S. patent application Ser. No.12/271,192 filed Nov. 14, 2008.

In addition, although the present embodiment is configured with top andbottom electrical contacts, the subcells may alternatively be contactedby means of metal contacts to laterally conductive semiconductor layersbetween the subcells. Such arrangements may be used to form 3-terminal,4-terminal, and in general, n-terminal devices. The subcells can beinterconnected in circuits using these additional terminals such thatmost of the available photogenerated current density in each subcell canbe used effectively, leading to high efficiency for the multijunctioncell, notwithstanding that the photogenerated current densities aretypically different in the various subcells.

As noted above, the present invention may utilize an arrangement of oneor more, or all, homojunction cells or subcells, i.e., a cell or subcellin which the p-n junction is formed between a p-type semiconductor andan n-type semiconductor both of which have the same chemical compositionand the same band gap, differing only in the dopant species and types,and one or more heterojunction cells or subcells. Subcell A, with p-typeand n-type InGaP is one example of a homojunction subcell.Alternatively, as more particularly described in U.S. patent applicationSer. No. 12/023,772 filed Jan. 31, 2008, the present invention mayutilize one or more, or all, heterojunction cells or subcells, i.e., acell or subcell in which the p-n junction is formed between a p-typesemiconductor and an n-type semiconductor having different chemicalcompositions of the semiconductor material in the n-type regions, and/ordifferent band gap energies in the p-type regions, in addition toutilizing different dopant species and type in the p-type and n-typeregions that form the p-n junction.

In some cells, a thin so-called “intrinsic layer” may be placed betweenthe emitter layer and base layer, with the same or different compositionfrom either the emitter layer or the base layer. The intrinsic layerfunctions to suppress minority-carrier recombination in the space-chargeregion. Similarly, either the base layer or the emitter layer may alsobe intrinsic or not-intentionally-doped (“ND”) over part or all of itsthickness.

The composition of the window or BSF layers may utilize othersemiconductor compounds, subject to lattice constant and band gaprequirements, and may include AlInP, AlAs, AlP, AlGaInP, AlGaAsP,AlGaInAs, AlGaInPAs, GaInP, GaInAs, GaInPAs, AlGaAs, AlInAs, AlInPAs,GaAsSb, AlAsSb, GaAlAsSb, AlInSb, GaInSb, AlGaInSb, AIN, GaN, InN,GaInN, AlGaInN, GaInNAs, AlGaInNAs, ZnSSe, CdSSe, and similar materials,and still fall within the spirit of the present invention.

While the invention has been illustrated and described as embodied in ainverted metamorphic multijunction solar cell, it is not intended to belimited to the details shown, since various modifications and structuralchanges may be made without departing in any way from the spirit of thepresent invention.

Thus, while the description of this invention has focused primarily onsolar cells or photovoltaic devices, persons skilled in the art knowthat other electronic and optoelectronic devices, such as, transistors,thermophotovoltaic (TPV) cells, photodetectors and light-emitting diodes(LEDS) are very similar in structure, physics, and materials tophotovoltaic devices with some minor variations in doping and theminority carrier lifetime. For example, photodetectors can be the samematerials and structures as the photovoltaic devices described above,but perhaps more lightly-doped for sensitivity rather than powerproduction. On the other hand LEDs and also be made with similarstructures and materials, but perhaps more heavily-doped to shortenrecombination time, thus radiative lifetime to produce light instead ofpower. Therefore, this invention also applies to photodetectors and LEDswith structures, compositions of matter, articles of manufacture, andimprovements as described above for photovoltaic cells.

Without further analysis, from the foregoing others can, by applyingcurrent knowledge, readily adapt the present invention for variousapplications. Such adaptations should and are intended to becomprehended within the meaning and range of equivalence of thefollowing claims.

1. A method of manufacturing a solar cell, comprising: providing asemiconductor carrier with a prepared bonding surface; providing asupport substrate; bonding the semiconductor carrier and the supportsubstrate to produce a composite structure; detaching the bulk of thesemiconductor carrier from the composite structure, leaving asemiconductor growth substrate on the support substrate; depositing asequence of layers of semiconductor material forming a solar cell on thesemiconductor growth substrate; mounting a surrogate second substrate ontop of the sequence of layers of semiconductor material forming thesolar cell; and removing the semiconductor growth substrate and leavingthe sequence of layers of semiconductor material forming the solar cell.2. The method of claim 1, wherein the semiconductor growth substrate isgallium arsenide or germanium.
 3. The method of claim 1, wherein bondingthe semiconductor carrier and the support substrate to produce thecomposite structure comprises molecularly bonding the prepared bondingsurface of the semiconductor carrier directly to a surface of thesupport substrate.
 4. The method of claim 1, wherein detaching the bulkof the semiconductor carrier from the composite structure comprises:implanting a species into the semiconductor carrier to form a defectlayer in the semiconductor carrier; bonding the defect layer of thesemiconductor carrier directly to the support substrate to produce thecomposite structure; and detaching the bulk of the semiconductor carrierfrom the composite structure, leaving the semiconductor growth substrateon the support substrate, the semiconductor growth substrate beingrelatively thin.
 5. The method of claim 4, wherein detaching the bulk ofthe semiconductor carrier from the composite structure comprises:annealing the composite structure at an elevated temperature to weakenthe semiconductor carrier at the defect layer; and detaching the bulk ofthe semiconductor carrier from the composite structure along the defectlayer after or during annealing of the composite structure.
 6. Themethod of claim 1, wherein the thickness of the semiconductor substrateis about 5 microns, and the thickness of the bulk of the semiconductorcarrier detached from the composite structure is in excess of 350microns.
 7. The method of claim 1, further comprising roughening theprepared bonding surface of the semiconductor carrier prior to bondingthe carrier and the support substrate.
 8. The method of claim 1, furthercomprising: (i) preparing a new bonding surface on the detached bulkportion of the semiconductor carrier to form a new semiconductorcarrier; (ii) providing a new support substrate; (iii) bonding the newsemiconductor carrier and the new support substrate to produce a newcomposite structure; (iv) detaching the bulk of the new semiconductorcarrier from the new composite structure, leaving a new semiconductorsubstrate on the new support substrate; and (v) depositing a sequence oflayers of semiconductor material forming a solar cell on the newsemiconductor substrate; and (vi) repeating steps (i) through (v) withthe detached bulk portion of the new semiconductor carrier.
 9. A methodas defined in claim 1, wherein the support substrate is sapphire orsapphire/spinel.
 10. A method as defined in claim 2, wherein the step ofdepositing a sequence of layers on the gallium arsenide growth substratecomprises: forming an upper first solar subcell having a first band gapon said gallium arsenide growth substrate; forming a middle second solarsubcell over said first solar subcell having a second band gap smallerthan said first band gap; forming a graded interlayer over said secondsolar subcell; forming a third solar subcell over said graded interlayerhaving a fourth band gap smaller than said second band gap such thatsaid third subcell is lattice mismatched with respect to said secondsubcell.
 11. The method as defined in claim 10, further comprisingforming a lower fourth solar subcell over said third subcell having afifth band gap smaller than said fourth band gap such that said fourthsubcell is lattice matched with respect to said third subcell.
 12. Themethod as defined in claim 10, wherein the upper subcell is composed ofInGa(Al)P, the second subcell is composed of an GaAs, GaInP, GaInAs,GaAsSb, or GaInAsN emitter region and a GaAs, GaInAs, GaAsSb, or GaInAsNbase region, and the third subcell is composed of a GaInAsP base andemitter.
 13. The method as defined in claim 11, wherein the fourthsubcell is composed of GaInAs base and emitter layers.
 14. The method asdefined in claim 10, wherein the graded interlayer is compositionallygraded to lattice match the second subcell on one side and the thirdsubcell on the other side and is composed of (In_(x)Ga_(1-x))_(y)Al_(1-y)As with x and y selected such that the band gap of the gradedinterlayer remains constant throughout its thickness.
 15. A method asdefined in claim 1, wherein the semiconductor carrier is galliumarsenide that is off-cut from the (001) crystal plane by at least 6°towards the (111)A plane.
 16. A method as defined in claim 1, furthercomprising removing the surrogate second substrate and leaving thesequence of layers of semiconductor material forming the solar cell.